Simpler ISA

I was looking to build a risc-v cpu with a 5-stage pipeline in Verilog to learn computer architecture and digital design. But after looking at the ISA for the RV32I, I realized that the instruction set is a little too complex for me right now and I might want to try something smaller before jumping to the risc-v implementation. Is there a smaller instruction set that perhaps utilizes 16-bits that I can do?

https://redd.it/1kkzq4e
@r_riscv

Kalman filter using risc 5 vector isa

we've been tasked to build the kalman filter using risc 5 vector isa. Has anyone ever done a project using risc 5 vector isa. If yes, can you please reach out and help

https://redd.it/1kkz4td
@r_riscv

RISC-V synth on Kickstarter
https://www.kickstarter.com/projects/andrewjohnmarch/m0ss-101-a-virtual-analog-monosynth

https://redd.it/1kl3yua
@r_riscv

An issue with vector intrinsics, could someone help me?

Hello everybody, this is my first time posting on Reddit but I have a problem that I can't seem to figure out.

I am trying to write a report about the effects of changing the value of the vector length and the value of the stride length on the performance of the RISCV architecture. To test this out, I cloned the RISCV GNU toolchain and built it so that it would have the vector extension with it and I made a little code that uses the header file riscv_vector.h, I made sure the path is correct and that the compiler is reading it properly, however, it always gives me an error of implicitly defined functions in the code, and I think this means that it found the declaration in the header file but did not find the implementation. Could someone please help me figure out what could be the problem? And also is ths he best way to go about testing the effects for my report, since I am not really well-versed in this subject I wouldn't know what is the best way to test it. Thanks in advance.

https://redd.it/1kl7rhe
@r_riscv

Bringing VisionFive 2 into 2025
https://cakehonolulu.github.io/open-source-ifying-the-visionfive-2/

https://redd.it/1klfvgj
@r_riscv

Ventana RV Summit Slides (SPECint2017 and Veyron V3)

https://redd.it/1klghgq
@r_riscv

New to Ripes – Where Should I Start?

Hey everyone,

I'm currently studying Computer Engineering and recently came across the Ripes program as part of my classes. It looks super interesting, but I’ll be honest—I’m a complete noob when it comes to it.

From what I understand, Ripes is used for visualizing how a processor works, especially in terms of pipelines and assembly instructions. I want to get a solid grasp of how to use it, not just to pass my classes, but to really understand what's going on under the hood.

My question is: where should I start?
Should I begin by reading documentation and learning the concepts first, or just jump into some YouTube tutorials and get a feel for it by watching others use it?

Also, any beginner-friendly resources or tips would be much appreciated!

Thanks in advance!

https://redd.it/1klkblj
@r_riscv

ALPHA-One Leverages RISC-V StarPro64 for Compact Local LLM Deployment
https://linuxgizmos.com/alpha-one-leverages-risc-v-starpro64-for-compact-local-llm-deployment/

https://redd.it/1km303k
@r_riscv

M5Stack Launches the Tablet-Like Tab5 HMI Module — Powered by Espressif's ESP32-P4
https://www.hackster.io/news/m5stack-launches-the-tablet-like-tab5-hmi-module-powered-by-espressif-s-esp32-p4-f39b216a79f6.amp

https://redd.it/1km9va7
@r_riscv

SiFive Partners with Kinara to Put Two RISC-V Cores and 40 TOPS of Ara-2 Compute on a USB Stick
https://www.hackster.io/news/sifive-partners-with-kinara-to-put-two-risc-v-cores-and-40-tops-of-ara-2-compute-on-a-usb-stick-5557cbb067ac.amp

https://redd.it/1km9thp
@r_riscv

Efficient sign extension on RISC-V
https://needlesscomplexity.substack.com/p/efficient-sign-extension-on-risc

https://redd.it/1kms5rm
@r_riscv

How to set up PMP for RV32I to give access to every available address?

I'm reading the specification and wondering, is it possible to configure PMP to give access to every possible memory location with just one TOR entry?

Let's say I have paging enabled so there are 34-bit physical addresses available.

If I set pmpaddr0 to 0xFFFF_FFFF then I make my highest physical address accessible 0x3_FFFF_FFFB (0xFFFFFFFF << 2 - 1) as available address must be 0 <= addr < pmpaddr0, so it makes last 4 bytes unavailable.

Am I right or am I missing something here?

EDIT:

To be fair, what made me look into documentation in the first place is source code for xv6, where they set up PMP as such:

// configure Physical Memory Protection to give supervisor mode

// access to all of physical memory.

w_pmpaddr0(0x3fffffffffffffull);

w_pmpcfg0(0xf);

which, isn't completely true, is it?


Link to xv6 source code:

https://github.com/mit-pdos/xv6-riscv/blob/riscv/kernel/start.c , lines 36 & 37.

https://redd.it/1kmtr8o
@r_riscv

Bare metal JavaScript on RISC-V
https://popovicu.com/posts/bare-metal-javascript-riscv/

https://redd.it/1kmypqv
@r_riscv

New learner needs suggestions


I recently completed a RISC-V CPU with a 5-stage pipeline (IF, ID, EX, MEM, WB) using Verilog.
It supports arithmetic (add, sub, mul), branching, memory access, and can execute C code compiled with GCC.
GitHub repo: https://github.com/SHAOWEICHEN000/RISCV_CPU

I’d love feedback or suggestions for optimization / synthesis.


https://redd.it/1kna7nc
@r_riscv

Milkv Duo S audio hat

I've built a milkv duo s audio hat with two mics, an accelerometer, fuel gauge, and jst connectors for both a speaker and a battery.

It will have slots for SPI if you needed to use it, and you can use dupont wires to connect every pin on this hat to a pi if you wanted to (not the prettiest thing in the world, but still)

If I put it up on a site for purchase, would anyone be interested in buying it?

https://redd.it/1kneb7h
@r_riscv

assembly (mul and mulh)

for MUL rd,rs1,rs2, i know that mul returns the lower half bits of the product and it doesn’t matter whether rs1 and rs2 are signed or unsigned since the result will be the same. but does anyone know why? is there some sort of formal proof or general case that explains why it’s the same lower bits

https://redd.it/1kng2ga
@r_riscv